Kyung Ki Kim ¹

Affiliations
1 School of Electronic and Electrical Engineering, Daegu University, Gyeongsan, KR

Abstract

As technology scales down, it has become one of the most critical issues in aging-tolerant nanoscale MOSFET circuit design to monitor the performance degradation of the circuits under aging stress conditions such as Negative-Bias-Temperature Instability (NBTI) and Hot-Carrier-Injection (HCI). Hence, this paper proposes a novel on-chip circuit to measure the delay degradation of stressed MOSFET digital circuits and digitalize the degradation for aging compensation. A 0.11μm CMOS technology has been used to implement and evaluate the proposed circuits.

Keywords

Aging Effect, Aging Prediction, Bias Temperature Instability, Hot Carrier Injection, Reliability.

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